1. Field of the Invention
This invention relates to a CD-ROM decoder used in a CD-ROM system in which a compact disc or laser disc is employed as a read only memory. The CD-ROM decoder is used for transferring CD-ROM data read out from a disc in response to a command from a host computer.
2. Description of Related Art
A CD-ROM system, which utilizes a compact disc used in a digital audio system as a read only memory (ROM) for digital data, has been known. In such a CD-ROM system, code error correction is carried out twice for CD-ROM data read out from the compact disc in order to enhance the reliability. More particularly, first error correction is carried out in the reproduction unit, and second error correction is performed in the CD-ROM decoder connected to the reproduction unit. Generally, the first error correction is the same processing as that for an audio CD player.
Typical structure of the conventional CD-ROM system is shown in FIG. 1. A pickup unit 2 receives reflected light of a laser beam irradiated to a compact disc 1, converts the intensity of the reflected light into a voltage signal representing the intensity value, and supplies the signal to an analog signal processing unit 3. The analog signal processing unit 3 reads out digital data written in the compact disc 1 from the input signal, and outputs, in series, the digital data having a format similar to the given format. The output from the analog signal processing unit 3 is connected to an input of a digital signal processing unit 4, which carries out processing of the digital data input from the analog signal processing unit 3 in accordance with the digital data format (CD format) to produce CD-ROM data. The signal processing in the digital signal processing unit 4 maintains compatibility with a digital audio CD system, and includes, for example, demodulation of 14 bit digital data to 8 bit data and code error detection/correction based on Reed-Solomon code. A CD-ROM decoder 5 provides another code error correction for the CD-ROM data fed from the digital signal processing unit 4 and transfers the CD-ROM data, which has substantially no errors, to the host computer. A buffer RAM 6 is connected to the CD-ROM decoder 5 to temporarily store the CD-ROM data, which has been supplied from the digital signal processing unit 4 to the CD-ROM decoder 5, for a given period. A control micro computer 7 controls operation of the analog signal processing unit 3, digital signal processing unit 4 and CD-ROM decoder 5 in accordance with the operation programs so that each unit carries out the respective processing at the correct time.
A typical data format for a sector of conventional CD-ROM data is shown in FIG. 2. The CD-ROM data output from the digital signal processing unit 4 shown in FIG. 1 is divided into a number of sectors, and each sector is 2352 bytes and consists of a synchronization signal (12 bytes), header (4 bytes) and user data (2336 bytes) as shown in FIG. 2. The synchronization signal for indicating a leading point of the sector is arranged as a fixed pattern at a leader portion of the sector. The 4 byte header is allocated for information representing an absolute period corresponding to the address on the disc (MIN, SEC and FRAME: each 1 byte) and for a mode identification code for defining the format of the data in the sector (MODE: 1 byte). The CD-ROM data not including the 12 byte synchronization signal portion (i.e. the remaining 2340 byte data portion) has been subjected to scramble processing so as to prevent occurrence of the same pattern as the synchronization signal. The 2340 byte data portion is descrambled to the original data before being input to the CD-ROM recorder 5.
FIG. 3 is a block diagram of the conventional CD-ROM decoder 5. A descramble circuit 11 provides descramble processing for the 2340 bytes of the 2352 bytes (1 sector) of CD ROM data input, disregarding the 12 byte synchronization signal, and outputs data which is recovered to be a given format. A write buffer 12 extracts 2336 bytes of data (hereinafter referred to as user data) from the data output from the descramble circuit 11 and writes the user data through a first data bus 16 into the buffer RAM 6. A header register 13 takes in 4 bytes of the data output from the descramble circuit 11 and transfers the header information via a second data bus 17 to the control micro computer 7. A synchronization signal detecting circuit 14 detects a 12 byte synchronization signal assigned to the leader portion of the respective sectors of the input data and supplies a timing signal representing the beginning of the sector's CD-ROM data input to an operation control circuit 25, details of which will be described below. When the synchronization signal is not detected, data showing the detection error is fed to the control micro computer 7 via the second data bus 17. An error flag register 15 extracts an error flag indicating that errors are still left after the error correction by the digital signal processing unit 4 arranged before the CD-ROM decoder 5 and transfers the information via the second data bus 17 to the control micro computer 7.
A write address generating circuit 18 generates a series of addresses at a constant cycling period to designate a write address of the CD-ROM data which is to be written into the buffer RAM 6 from the write buffer 12. A leading address generating circuit 19 receives an address of the buffer RAM 6, to which the leader portion of the respective sectors is to be written, from the address generating circuit 18. After keeping the received addresses until completion of the writing operation for a sector of the CD-ROM data, the leading address generating circuit 19 feeds the addresses to the first data bus 16. The leading addresses are also fed to the control micro computer 7 via the second data bus 17 so as to produce preset data for a transfer address generating circuit 21. An error correction circuit 20 takes in the leading address data via the first data bus 16 and sequentially reads out, based on the address data, the CD-ROM data which was written into the buffer RAM 6. The error correction circuit 20 then detects and corrects a code error on the basis of the error detection code (EDC) and error correction code (ECC), which have been set in the user data. When the data has been subjected to given error correction processing in the above described manner, it is again written into the buffer RAM 6.
The transfer address generating circuit 21 is loaded with the preset data corresponding to the leading address of the buffer RAM 6, at which time the reading out of the CD-ROM data begins. In response to the command from the transfer trigger generating circuit 22, the transfer address generating circuit 21 generates a series of addresses beginning from an address corresponding to the preset data. The generated addresses are fed via the first data bus 16 to the buffer RAM 6 and used for the designation of the readout address of the CD-ROM data which has been subjected to the error correction processing. A transfer bytes counter 23 is loaded with preset data representing the CD-ROM data to be read out from the buffer RAM 6 and then decrements (counts down) the preset data value every time a sector of the CD-ROM data is read out from the buffer RAM 6. At the point when a given count is completed, the counter 23 supplies a stop command to the transfer trigger generating circuit 22. A transfer buffer 24 receives, via the first data bus 16, the CD-ROM data which has been read out in accordance with the address generated by the transfer address generating circuit 21 and transfers the data to the host computer. Each preset data loaded on the transfer address generating circuit 21 and transfer bytes counter 23, respectively, is generated by the control micro computer 7 based on the leading address fed from the leading address generating circuit 19 and a transfer command given by the host computer.
The operation control circuit 25 counts the time period taken for the completion of error correction made by the error correction circuit 20, on the basis of a timing signal from the synchronization signal detecting circuit 14 and generates another timing signal indicating the completion of the error correction operation. The error correction processing is carried out inside the error correction circuit 20 after taking in a sector of CD-ROM data from the buffer RAM 6, during which the next one sector of CD-ROM data is being written in the buffer RAM 6.
An interrupt command generating circuit 26 receives either the timing signal from the operation control circuit 25 or the stop command from the transfer bytes counter 23 and feeds an interrupt command to the control micro computer 7. In response to the interrupt command, the control micro computer 7, which carries out the operation control for the analog signal processing unit 3 and digital signal processing unit 4 on a time sharing basis, suspends the operation which is being carried out at that point and allows the CD-ROM decoder 5 to perform the next operation. In other words, by interrupting the current operation in response to the interrupt command, the control micro computer 7 may drive the transfer trigger generating circuit 22 to start the data transfer from the buffer RAM 6 to the host computer.
In this CD-ROM system, header information in each sector is repeatedly extracted and fed to the control micro computer 7. Based on the address information contained in the header information, a sector currently required by the host computer is detected.
However, various CD-ROM data formats, CD-ROM XA standard and Mode-2 format used in CD-I, employ an error detection/correction code not intended for the header. When using these formats, the header is not protected against errors at the stage of error correction by the CD-ROM decoder 5. Therefore, the header data reliability is inferior to the user data. To overcome this problem, the control micro computer 7 determines whether or not the header information is correct, with reference to the error flag transferred from the error flag register 15 and gives an operation command to the CD-ROM decoder 5 based on the determination.
However, in the control micro computer 7, since the determination of the accuracy of the header information and the detection of address information are carried out in parallel to the operation control for the analog signal processing unit 3 and digital signal processing unit 4, the load on the control micro computer 7 becomes heavy. Furthermore, when errors are contained in a header portion, inference of the correct information contained in the header portion is required, which further increases the burden to the control micro computer 7. Consequently, it becomes difficult to speed up the control operation of the control micro computer 7, which limits the amount of data that can be processed by the CD-ROM decoder 5.